Hardware-Level
Pong Game Engine
Verilog HDL Implementation & VGA Controller Design
A real-time arcade engine built entirely from scratch using Verilog. Unlike software-based games, this project implements game logic, VGA synchronization, and PS/2 keyboard interfacing directly through digital circuit design on an FPGA, ensuring zero-latency performance.
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Custom VGA Controller
Designed a synchronization generator from scratch to drive 640x480 video output with precise horizontal and vertical timing.
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Hardware Logic & FSM
Implemented game states (Start, Play, Goal, Reset) using a robust Finite State Machine (FSM) architecture.
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Real-time Collision Detection
Developed low-latency arithmetic logic to calculate ball trajectories and paddle intersections in every clock cycle.
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Peripheral Interfacing
Integrated PS/2 keyboard protocol to allow responsive user control through hardware interrupts/sampling.
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Resource Optimization
Optimized RTL code for FPGA deployment, ensuring efficient utilization of Look-Up Tables (LUTs) and registers.